module RegIdEx (    
    input [1:0]  Branch_in,      
    input [1:0]  MemtoReg_in,    
    input [3:0]  AluOp_in,  
    input        MemWrite_in,   
    input        AluSrc_in,      
    
     
    input        RegWrite_in,    
    input [1:0]  Jump_in,        
    input        Sign_in,
    input [1:0]  DataType_in,
    input        DataSign_in,
    input        MemRead_in,
    input [31:0] pc_in,
    input [31:0] data_rs_in,
    input [31:0] data_rt_in,
    input [15:0] immediate_in,
    input [4:0]  instr1_in,
    input [31:0] instr,
    input stall,
    input clk,

     
    output reg [1:0]   Branch_out,      
    output reg [1:0]   MemtoReg_out,    
    output reg [3:0]   AluOp_out,  
    output reg         MemWrite_out,    
    output reg         AluSrc_out,      
   

    output reg         RegWrite_out,    
    output reg [1:0]   Jump_out,        
    output reg         Sign_out,
    output reg [31:0]  pc_out,
    output reg [31:0]  data_rs_out,
    output reg [31:0]  data_rt_out,
    output reg [15:0]  immediate_out,
    output reg [4:0]   instr1_out,
    output reg [31:0]  instr_out,
    output reg [1:0]   DataType_out,
    output reg         DataSign_out,
    output reg         MemRead_out
  

);
    
    
    always @(posedge clk) begin
        if(!stall)
        begin
            Branch_out   <= Branch_in;
            MemtoReg_out  <= MemtoReg_in;
            AluSrc_out  <= AluSrc_in;
            AluOp_out <= AluOp_in;
            MemWrite_out <= MemWrite_in;
            RegWrite_out <= RegWrite_in;
            Jump_out <= Jump_in;
            Sign_out <= Sign_in;
            DataType_out <= DataType_in;
            DataSign_out <= DataSign_in;
            pc_out <= pc_in;
            data_rs_out <= data_rs_in;
            data_rt_out <= data_rt_in;
            immediate_out <= immediate_in;
            instr1_out <= instr1_in;
            instr_out <= instr;
            MemRead_out = MemRead_in;
        end
        else
        begin
            MemWrite_out <= 1'b0;
            RegWrite_out <= 1'b0;
            MemRead_out = 1'b0;
        end
    end

endmodule //reg_id_ex